Demonstration of P-Type Stack-Channel Ternary Logic Device Using Scalable Dntt Patterning Process

Authors

Yongsu Lee
Heejin Kwon
Seung-Mo Kim
Ho-In Lee
Kiyung Kim
Hae-Won Lee
So-Young Kim
Hyeon Jun Hwang
Byoung Hun Lee

Publication Date

3-9-2023

Journal

Nano Convergence

Abstract

A p-type ternary logic device with a stack-channel structure is demonstrated using an organic p-type semiconductor, dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). A photolithography-based patterning process is developed to fabricate scaled electronic devices with complex organic semiconductor channel structures. Two layers of thin DNTT with a separation layer are fabricated via the low-temperature deposition process, and for the first time, p-type ternary logic switching characteristics exhibiting zero differential conductance in the intermediate current state are demonstrated. The stability of the DNTT stack-channel ternary logic switch device is confirmed by implementing a resistive-load ternary logic inverter circuit.

Keywords

Organic semiconductor, Photolithography, Ternary logic, Stack-channel, Zero differential conductance